use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity countern is
generic (N: integer:=24);
port
(
clk:in std_logic;
reset:in std_logic;---------------------------復(fù)位端
enable:in std_logic;--------------------------使能端
q:out integer range 0 to N-1
);
end entity countern;
architecture bhv of countern is
begin
process (clk)
variable cnt : integer range 0 to 23;
begin
if reset = '1' then cnt:= 0;--reset為1時計數(shù)器復(fù)位
elsif enable = '1'then--使能端為1時計數(shù)器正常工作
if(clk'event and clk='1') then--時鐘上升沿到來時計數(shù)
if(cnt<23) then--加法計數(shù)
cnt:= cnt+1;
else
cnt := 0;
end if;
end if;
end if;
q <= cnt; ----輸出計數(shù)值
end process;
end bhv;
仿真波形：
