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標題: 三角波矩形波正弦波VHDL源程序 [打印本頁]

作者: 18538208295 時間: 2018-11-29 18:26
標題: 三角波矩形波正弦波VHDL源程序
//三角波
//clk:時鐘信號
//reset：復位信號
//San_out：三角波輸出
module san(clk,rest,san_out);
input clk,reset;
output[7:0 ] san_out;
reg[7:0] san_out;
reg[7:0] num;    //計數器
reg reg_1;    //加減控制
always@(posedgec clk or posedge reset)
begin
if(reset)
   num<=0;
else if(reg_1 == 0)
begin
if(num = = 8’b11111000)//取正32個點
begin
   num<=255;
reg_1<=1;
end
else
   num<=0;
   reg_1<=0;
end
else
   begin
      num<=num-8;    //取負32個點-8取點
end
end
always@（num）
begin
   san_out<=num;
end
endmodule

//正弦波
//clk:時鐘信號
//reset：復位信號
//sin_out：三角波輸出
module sin(clk,rest,sin_out);
input clk_1,reset;
output[7:0 ] sin_out;
reg[7:0] sin_out;
reg[6:0] num;    //計數器
always@(posedgec clk or posedge reset)
begin
   if(reset)
      sin_out<=0;       //取64個點
   elseif(num = =63)
      num<=0;
   else
      um<=num+1;
   case(num)
   0:sin_out<=255;
   1:sin_out<=254;
2:sin_out<=252;
   3:sin_out<=216;
   4:sin_out<=245;
   5:sin_out<=239;
   6:sin_out<=233;
   7:sin_out<=225;
   8:sin_out<=217;
   9:sin_out<=207;
   10:sin_out<=197;
11:sin_out<=186;
12:sin_out<=174;
13:sin_out<=162;
14:sin_out<=150;
15:sin_out<=137;
16:sin_out<=124;
17:sin_out<=112;
18:sin_out<=99;
19:sin_out<=87;
20:sin_out<=75;
21:sin_out<=64;
22:sin_out<=53;
23:sin_out<=43;
24:sin_out<=34;
25:sin_out<=26;
26:sin_out<=19;
27:sin_out<=13;
28:sin_out<=8;
29:sin_out<=4;
30:sin_out<=1;
31:sin_out<=0;
32:sin_out<=0;
33:sin_out<=1;
34:sin_out<=4;
35:sin_out<=8;
36:sin_out<=13;
37:sin_out<=19;
38:sin_out<=26;
39:sin_out<=34;
40:sin_out<=43;
41:sin_out<=53;
42:sin_out<=64;
43:sin_out<=75;
44:sin_out<=87;
45:sin_out<=99;
46:sin_out<=112;
47:sin_out<=124;
48:sin_out<=137;
49:sin_out<=150;
50:sin_out<=162;
51:sin_out<=174;
52:sin_out<=186;
53:sin_out<=197;
54:sin_out<=207;
55:sin_out<=217;
56:sin_out<=225
57:sin_out<=233;
58:sin_out<=239;
59:sin_out<=245;
60:sin_out<=249;
61:sin_out<=252;
62:sin_out<=254;
63:sin_out<=255;
   default:sin_out<=8’bx;
   endcase
end
endmodule
//方波
//clk:時鐘信號
//reset：復位信號
//fang_out：三角波輸出
module fang(clk,rest,fang_out);
input clk,reset;
output[7:0 ] fang_out;
reg[7:0] fang_out;
reg[5:0] num;
reg reg_2;
always@(posedgec clk or posedge reset)
begin
   if(reset)
      reg_2<=0;
      elseif(num<31) //分頻32個時間單位為半個周期
            num<=num+1;
            else
               begin
                  num<=0;
                  reg_2<=~reg_2;
               end
            case(reg_2)
               0:fang_out<=255; //表示高電平如果用1 從0000 0000 到00000001 對電壓進行64分壓太小
               1:fang_out<=0;
            endcase
         end
endmodule
//控制模塊
//wave_out 輸出波形
module control(s1,s2,san,sin,fang,wave_out);
input s1,s2;
input[7:0]san,sin,fang;
output[7:0]wave_out;
reg[7:0] wave_out;
reg s1,s2;
always@( san or sin or fang)
begin
case({s1,s2})
   2’b00:wave_out= san;
   2’b01:wave_out= sin;
   2’b10:wave_out= fang;
   2’b11:wave_out = 0;    //第四種情況輸出為0
default:wave_out=8’bx;
endcase
end
endmodule
//頻率控制模塊
module div_clk(c1,c2,reset,,clk_out);
inputc1,c2, reset;
input[10:0] count;
reg clk;
always@(c1or c2 or posedge reset)
   begin
      if(reset)
clk_out<=0;
      case({c1,c2})
      2;b00：clk = ~clk ;#5;
2;b01：clk = ~clk ;#50;
2;b10：clk = ~clk ;#500;
2;b11：clk =~clk ;#5000;
   endcase
         clk_out= clk;
   end
endmodule
//最后組合程序
modulesignal_generator(CLK,reset,san,sin,fang,output);
input CLK,reset;
input san,sin,fang;
output[7:0]output;
wire CLK_1;
wire[7:0] san,sin,fang
div_ctrlU1(reset(reset) ,clk_out(CLK_1));
contrl U2(s1(S1),s2(S2),san(san),sin(sin),fang(fang),wave_out(output));
san U3(clk(CLK_1),reset(reset),san _out(san));
sin U4(clk(CLK_1),reset(reset),sin_out(sin));
fang U5(clk(CLK_1),reset(reset),fang_out(fang));
endmodule

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