標題: 基于fpga的方波，三角波信號發生器 [打印本頁] 作者: 晉子奇 時間: 2018-12-29 14:22 標題: 基于fpga的方波，三角波信號發生器 LIBRARY IEEE;-- 選擇器USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Xuanzeqi IS PORT ( sel: in std_logic_vector(1 downto 0); d1,d2:in std_logic_vector(7 downto 0); clk,reset:in std_logic;q:out std_logic_vector(7 downto 0)); END ENTITY Xuanzeqi; ARCHITECTURE behave OF Xuanzeqi IS BEGIN PROCESS(sel) BEGIN CASE sel IS WHEN "00"=>q<=d1;-- 方波
WHEN "11"=>q<=d2;-- 三角波
WHEN OTHERS=>null; END CASE; END PROCESS; END ARCHITECTURE behave; LIBRARY IEEE;-- 方波USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Fangbo IS PORT ( clk,reset:in std_logic; q: out std_logic_vector(7 DOWNTO 0)); END ENTITY Fangbo; ARCHITECTURE behave OF Fangbo IS SIGNAL temp : std_logic ; BEGIN PROCESS(clk,reset) VARIABLE tmp: std_logic_vector(7 downto 0); BEGIN IF reset='0' THEN temp<='0'; ELSIF rising_edge(clk) THEN IF tmp="11111111" THEN tmp:="00000000"; ELSE tmp:=tmp+1; END IF; IF tmp<="10000000" THEN temp<='1'; ELSE temp<='0'; END IF; END IF; END PROCESS; PROCESS(clk,temp) BEGIN IF rising_edge(clk) THEN IF temp='1' THEN q<="10000000"; -- 占空比？ELSE q<="11111111"; END IF; END IF;
END PROCESS; END ARCHITECTURE behave;
LIBRARY IEEE;-- 三角波USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Sanjiaobo IS PORT ( clk,reset:in std_logic; q:out std_logic_vector(7 downto 0)); END ENTITY Sanjiaobo; ARCHITECTURE behave OF Sanjiaobo IS BEGIN PROCESS(clk,reset) VARIABLE temp1:std_logic_vector(7 downto 0); VARIABLE temp2:std_logic; BEGIN IF reset='0' THEN temp1:="00000000"; ELSIF rising_edge(clk) THEN IF temp2='0' THEN IF temp1="11111110" THEN temp1:="11111111" ; temp2:='1'; ELSE temp1:=temp1+1; END IF; ELSE IF temp1="00000001" THEN temp1:="00000000"; temp2:='0'; ELSE temp1:=temp1-1; END IF; END IF; END IF; q<=temp1; END PROCESS; END ARCHITECTURE behave;
LIBRARY IEEE;-- 函數發生器USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY hanshu IS PORT ( clock,sw:in std_logic; clr:IN STD_LOGIC; s:IN STD_LOGIC_VECTOR ( 1 DOWNTO 0); qq:OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END ENTITY hanshu; ARCHITECTURE behave of hanshu IS component Xuanzeqi PORT ( sel: in std_logic_vector(1 downto 0); d1,d2:in std_logic_vector(7 downto 0); clk,reset:in std_logic;q:out std_logic_vector(7 downto 0)); END component Xuanzeqi; component Fangbo port ( clk,reset:in std_logic; q: out std_logic_vector(7 downto 0)); end component Fangbo; component Sanjiaobo PORT ( clk,reset:in std_logic; q:out std_logic_vector(7 downto 0)); end component Sanjiaobo; SIGNAL t1, t2: std_logic_vector ( 7 downto 0); SIGNAL clk,clk1: std_logic;
begin u0: xuanzeqi port map ( sel =>s, d1 =>t1, d2=>t2,clk=>clk1,reset=>clr,q =>qq) ; u1: Fangbo port map ( clk =>clk1, reset =>clr,q=>t1);
u2: Sanjiaobo port map ( clk =>clk1, reset=>clr, q =>t2);
process(clock)beginif clock'event and clock='1' thenclk<=not clk;end if;end process;
process(sw,clock)beginif sw='1' thenclk1<=clk;elseclk1<=clock;end if;end process;
end behave;