標題: FPGA/CycloneIV E/EP4CE115F29C8開發板管腳配置 [打印本頁] 作者: xiaoliu 時間: 2014-11-10 15:19 標題: FPGA/CycloneIV E/EP4CE115F29C8開發板管腳配置 # Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.# Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version
# File: E:\SVN\DE2_115\trunk\test\de2_115_golden_sopc\de2_115_golden_sopc.csv
# Generated on: Fri Jun 18 14:51:18 2010
# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.
To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved 時鐘晶振連接：50MHz、27MHz
clk 50MHz Crystal Input,Pin_Y2;
CLOCK2_50,Input,PIN_AG14,3,B3_N0,3.3-V LVTTL,
CLOCK3_50,Input,PIN_AG15,4,B4_N2,3.3-V LVTTL,
CLOCK_50,Input,PIN_Y2,2,B2_N0,3.3-V LVTTL,
SEG,SEG2:out std_logic_vector(6 downto 0));
end;
Architecture dd of court60 is
signal qq:std_logic_vector(24 downto 0);
SIGNAL T:std_logic_vector(9 downto 0);
SIGNAL SEG1:std_logic_vector(6 downto 0);
signal qq1,qq2:std_logic_vector(3 downto 0);
signal cp:std_logic;
procedure sum( x:in std_logic_vector(3 downto 0);
Y:out std_logic_vector(6 downto 0))is
begin
case x is
when"0000"=>y:="0111111";
when"0001"=>y:="0000110";
when"0010"=>y:="1011011";
when"0011"=>y:="1001111";
when"0100"=>y:="1100110";
when"0101"=>y:="1101101";
when"0110"=>y:="1111101";
when"0111"=>y:="0000111";
when"1000"=>y:="1111111";
when"1001"=>y:="1101111";
when others=>y:=Null;
end case;
end sum;
begin
Process(clk)
begin
if clk'event and clk='1' then qq<=qq+1;T<=T+1;
if qq=24999999 then
qq<="0000000000000000000000000";
cp<=not cp;
end if;
end if;
if cp'event and cp='1' then
qq1<=qq1+1;
if qq1=9 then qq1<="0000";qq2<=qq2+1;
end if;
if qq2=5 and qq1=9 then qq2<="0000";
end if;
end if;
end process;
Q<=qq1;
Process(qq1,qq2)
variable y1,y2:std_logic_vector(6 downto 0);
begin
sum(qq1,y1);
sum(qq2,y2);
SEG<=not y1;
SEG2<=not y2;
end process;
end;