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標(biāo)題: VHDL 八位二進(jìn)制數(shù)減法器 [打印本頁]

作者: xiaoliu 時(shí)間: 2014-11-10 15:30
標(biāo)題: VHDL 八位二進(jìn)制數(shù)減法器
接上篇：http://www.zg4o1577.cn/bbs/dpj-28500-1.html
五、八位二進(jìn)制數(shù)減法器
   一）、不帶符號
該減法器只能大數(shù)減小數(shù)，不帶正負(fù)號，且運(yùn)算在時(shí)鐘脈沖上升沿到來時(shí)進(jìn)行計(jì)算。
Library ieee;
Use ieee.std_logic_1164.all;
Entity jianfaqi8 is
Port(a,b:in std_logic_vector(7 downto 0);
   CLK:in std_logic;
   S:out std_logic_vector(7 downto 0);
   co:out std_logic);
end jianfaqi8;
Architecture add of jianfaqi8 is
signal a1,b1:std_logic_vector(7 downto 0);
component adder8 is
Port(a,b:in std_logic_vector(7 downto 0);
   cin:in std_logic;
   S:out std_logic_vector(7 downto 0);
   co:out std_logic);
end component;
begin
process(a,b,CLK)
begin
if CLK'event and CLK='1' then
a1<=a;
b1<=b;
end if;
end process;
U:adder8 port map(a1,(not b1),'1',S,co);
end;

二）帶符號
可以大減小，也可小減大，輸出正負(fù)的計(jì)算結(jié)果
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity jianfaqi8 is
Port(a,b:in std_logic_vector(7 downto 0);
   CLK:in std_logic;
   S:out std_logic_vector(7 downto 0);
   co:out std_logic);
end jianfaqi8;
Architecture add of jianfaqi8 is
signal a1,b1,S1,S2,S3:std_logic_vector(7 downto 0);
signal c1,c2:std_logic;
component adder8 is
Port(a,b:in std_logic_vector(7 downto 0);
   cin:in std_logic;
   S:out std_logic_vector(7 downto 0);
   co:out std_logic);
end component;
begin
process(a,b,CLK)
begin
if CLK'event and CLK='1' then
   a1<=a;b1<=b;
end if;
end process;
U:adder8 port map(a1,(not b1),'1',S1,c1);
c2<=c1 xor '1';
co<=c2;
Process(S1,c1)
begin
  if c2='0' then
   S<=S1;
else
   S2<= S1-1;
   S<=not S2;
  end if;
end process;
end;

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