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標題: 計數器——VHDL源碼 [打印本頁]

作者: liuda 時間: 2015-1-23 21:36
標題: 計數器——VHDL源碼
本來這段代碼早就應該公布了的，可是我直到昨天才在開發板上進行調試，剛開始調試結果不是我想要的結果，不過仔細跟住結果想一下就找到問題所在，并很快解決調試通過，呵呵，挺高興的。這段代碼中是循環掃描數碼管位，所以最后一個文件是一個譯碼的文件，中間是進行按鍵處理并顯示的文件，第一個文件是將譯碼和按鍵處理顯示的例化文件啦。
///////////////cout10.vhd文件
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cout10 is
port(
      clk_in,rest_in:in std_logic;
      clk_key_in:in std_logic;--按鍵
      clk_md_in:in std_logic_vector(2 downto 0);--加模式位--000 加1 --001 加10 010 加100 011 加1000
      bt_out:out std_logic_vector(3 downto 0);--數碼管位選
      cout:out std_logic_vector(6 downto 0)
      );
end;

architecture lammy02 of cout10 is
      component showled
            port(
                     indata:in std_logic_vector(3 downto 0);
                     outdata:out std_logic_vector(6 downto 0)
                     );
      end component showled;
      component cnt10
            port(
                     rest,clk:in std_logic;
                     clk_key:in std_logic;--按鍵
                     clk_md:in std_logic_vector(2 downto 0);--加模式位--000 加1 --001 加10 010 加100 011 加1000
                     bt:out std_logic_vector(3 downto 0);--數碼管位選
                     cout1:out std_logic_vector(3 downto 0)--個位
            );
      end component cnt10;
                     signal d_cout1:std_logic_vector(3 downto 0);
      begin
            u1: cnt10 port map (clk=>clk_in,rest=>rest_in,clk_key=>clk_key_in,clk_md=>clk_md_in,bt=>bt_out,cout1=>d_cout1);
            u2: showled port map (indata=>d_cout1,outdata=>cout);
end;

/////////////////////showled.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity showled is
port(
      indata:in std_logic_vector(3 downto 0);
      outdata:out std_logic_vector(6 downto 0)
      );
end;

architecture lammy01 of showled is
--signal in_data:std_logic_vector(3 downto 0);
begin
      process(indata)
      begin
            case indata is
            when "0000" => outdata<="0111111";--0
            when "0001" => outdata<="0000110";--1
            when "0010" => outdata<="1011011";--2
            when "0011" => outdata<="1001111";--3
            when "0100" => outdata<="1100110";--4
            when "0101" => outdata<="1101101";--5
            when "0110" => outdata<="1111101";--6
            when "0111" => outdata<="0000111";--7
            when "1000" => outdata<="1111111";--8
            when "1001" => outdata<="1101111";--9
            when others => null;
            end case;
      end process;
end;

///////////////cnt10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt10 is
port(
      rest,clk:in std_logic;
      clk_key:in std_logic;--按鍵
      clk_md:in std_logic_vector(2 downto 0);--加模式位--000 加1 --001 加10 010 加100 011 加1000

      bt:out std_logic_vector(3 downto 0);--數碼管位選
      cout1:out std_logic_vector(3 downto 0)--個位
      );
end;

architecture lammy02 of cnt10 is
      type state is(s0,s1,s2,s3);
      signal led_state:state;
      signal outdata_1,outdata_2,outdata_3,outdata_4:std_logic_vector(3 downto 0):="0000";
begin

lammy_01:process(rest,clk,led_state)
      begin
            if rest='1' then cout1<="0000";led_state<=s0;
            elsif clk'event and clk='1' then
            case led_state is
                     when s0 => bt<="1000";cout1<=outdata_1;led_state<=s1;
                     when s1 => bt<="0100";cout1<=outdata_2;led_state<=s2;
                     when s2 => bt<="0010";cout1<=outdata_3;led_state<=s3;
                     when s3 => bt<="0001";cout1<=outdata_4;led_state<=s0;
            end case;
            end if;
      end process;
lammy_02:process(clk_key)
      variable cout_1,cout_2,cout_3,cout_4:std_logic_vector(3 downto 0);
      begin
            if rising_edge(clk_key) then
                     if clk_md="000" then
                              if cout_1="1001" and cout_2="1001" and cout_3="1001" and cout_4="1001"
                                    then cout_1:="1001" ; cout_2:="1001" ; cout_3:="1001" ; cout_4:="1001";
                                    elsif cout_1="1001" and cout_2="1001" and cout_3="1001" then cout_4:=cout_4+1;cout_1:="0000";cout_2:="0000";cout_3:="0000";
                                             elsif cout_1="1001" and cout_2="1001" then cout_3:=cout_3+1;cout_1:="0000";cout_2:="0000";
                                                      elsif cout_1="1001" then cout_2:=cout_2+1;cout_1:="0000";
                                                            else cout_1:=cout_1+1;
                              end if;
                     elsif clk_md="001" then
                              if cout_2="1001" and cout_3="1001" and cout_4="1001"
                                    then cout_2:="1001" ; cout_3:="1001" ; cout_4:="1001";
                                    elsif cout_2="1001" and cout_3="1001" then cout_4:=cout_4+1;cout_2:="0000";cout_3:="0000";
                                             elsif cout_2="1001" then cout_3:=cout_3+1; cout_2:="0000";
                                             else cout_2:=cout_2+1;
                              end if;
                     elsif clk_md="010" then
                              if cout_3="1001" and cout_4="1001"
                                    then cout_3:="1001" ; cout_4:="1001";
                                    elsif cout_3="1001" then cout_4:=cout_4+1;cout_3:="0000";
                                    else cout_3:=cout_3+1;
                              end if;
                     elsif clk_md="011" then
                              if cout_4="1001" then cout_4:="1001";
                              else cout_4:=cout_4+1;
                              end if;
                     end if;
            end if;
            outdata_1<=cout_1;
            outdata_2<=cout_2;
            outdata_3<=cout_3;
            outdata_4<=cout_4;
      end process;
end;

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