if (I2C_GET_TIMEOUT_FLAG(I2C1))
{
I2C_ClearTimeoutFlag(I2C1);
}
else
{
if (i2c1_read)
{
switch (u32Status)
{
case 0x08:
//Write SLA+W to Register I2CDAT
I2C_SET_DATA(I2C1, (i2c1_addr << 1));
I2C_SET_CONTROL_REG(I2C1, I2C_SI);
break;
case 0x18:
//SLA+W has been transmitted and ACK has been received
I2C_SET_DATA(I2C1, i2c1_reg);
I2C_SET_CONTROL_REG(I2C1, I2C_SI);
break;
case 0x20:
//SLA+W has been transmitted and NACK has been received
I2C_SET_CONTROL_REG(I2C1, I2C_STA | I2C_STO | I2C_SI);
break;
case 0x28:
I2C_SET_CONTROL_REG(I2C1, I2C_STA | I2C_SI);
break;
case 0x10:
//Repeat START has been transmitted and prepare SLA+R
I2C_SET_DATA(I2C1, (i2c1_addr << 1) | 0x01); //Write SLA+R to Register I2CDAT
I2C_SET_CONTROL_REG(I2C1, I2C_SI);
break;
case 0x40:
//SLA+R has been transmitted and ACK has been received
I2C_SET_CONTROL_REG(I2C1, I2C_SI);
break;
case 0x58:
//DATA has been received and NACK has been returned
case 0x08: //START has been transmitted and prepare SLA+W
I2C_SET_DATA(I2C1, (i2c1_addr << 1)); //Write SLA+W to Register I2CDAT
I2C_SET_CONTROL_REG(I2C1, I2C_SI);
break;
case 0x18: // SLA+R has been transmitted and ACK has been received
I2C_SET_DATA(I2C1, i2c1_reg);
I2C_SET_CONTROL_REG(I2C1, I2C_SI);
break;
case 20:
I2C_SET_CONTROL_REG(I2C1, I2C_STA | I2C_STO | I2C_SI);
break;
case 0x28: //DATA has been received and NACK has been returned
I2C_SET_DATA(I2C1, i2c1_data);
I2C_SET_CONTROL_REG(I2C1, I2C_STO | I2C_SI);
i2c1_done = 1;
break;
}
}
}
u32Status = I2C_GET_STATUS(I2C1);
}