在制作數(shù)字時鐘之前，先要熟悉 用vhdl實現(xiàn)74LS161十進制計數(shù)器http://www.zg4o1577.cn/mcu/2233.html
然后在編寫時鐘描述語言
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity timer24 is
   port(CP,CR:IN STD_LOGIC;
        AS0,BS0,CS0,DS0,ES0,FS0,GS0,AS1,BS1,CS1,DS1,ES1,FS1,GS1:OUT STD_LOGIC;
        AM0,BM0,CM0,DM0,EM0,FM0,GM0,AM1,BM1,CM1,DM1,EM1,FM1,GM1:OUT STD_LOGIC;
        AH0,BH0,CH0,DH0,EH0,FH0,GH0,AH1,BH1,CH1,DH1,EH1,FH1,GH1:OUT STD_LOGIC);
END TIMER24;
architecture TIMER of TIMER24 is
signal H1,H0,M1,M0,S1,S0:std_logic_vector(3 downto 0);
SIGNAL C0,C1,C2,C3,C4,C5:  std_logic  ;
COMPONENT  court161  IS                               
 port( clk,CTT,CTP,LD,CR:in std_logic;
               D3,D2,D1,D0: in  std_logic;                 
               Q:out std_logic_VECTOR(3 DOWNTO 0);
               Co: out std_logic);
end COMPONENT;
COMPONENT  QDLED7  IS
 PORT(DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       a,b,c,d,e,f,g:out std_logic);
  end COMPONENT;                          
 begin
  U0:court161 PORT MAP(CP,'1','1','1',CR,'0','0','0','0',S0,C0);
  U1:court161 PORT MAP(C0,'1','1',(NOT(S1(2)AND S1(0))),CR,'0','0','0','0',S1,C1);
  U2:court161 PORT MAP((NOT(S1(2)AND S1(0))),'1','1','1',CR,'0','0','0','0',M0,C2);
  U3:court161 PORT MAP(C2,'1','1',(NOT(M1(2)AND M1(0))),CR,'0','0','0','0',M1,C3);
  U4:court161 PORT MAP(C3,'1','1','1',(CR AND(NOT(H1(1) AND H0(2)))),'0','0','0','0',H0,C4);
  U5:court161 PORT MAP(C4,'1','1',(NOT H1(1)),(CR AND(NOT(H1(1) AND H0(2)))),'0','0','0','0',H1,C5);
  U6:QDLED7   PORT MAP(S0,AS0,BS0,CS0,DS0,ES0,FS0,GS0);
  U7:QDLED7   PORT MAP(S1,AS1,BS1,CS1,DS1,ES1,FS1,GS1);
  U8:QDLED7   PORT MAP(M0,AM0,BM0,CM0,DM0,EM0,FM0,GM0);
  U9:QDLED7   PORT MAP(M1,AM1,BM1,CM1,DM1,EM1,FM1,GM1);
  U10:QDLED7   PORT MAP(H0,AH0,BH0,CH0,DH0,EH0,FH0,GH0);
  U11:QDLED7   PORT MAP(H1,AH1,BH1,CH1,DH1,EH1,FH1,GH1);
  END;
接上數(shù)碼管，和脈沖信號發(fā)生器，必要時要分頻，分成脈沖周期為1秒的脈沖周期方可。數(shù)碼管的驅(qū)動程序: http://www.zg4o1577.cn/mcu/2234.html  
 
   一般電路里的晶振頻率都很高，在設計秒表或鐘表時，需要將頻率很高的脈沖變成頻率為1Hz的脈沖，就可作為計時的標準單位，這個過程叫分頻，下面是將6MHz的頻率分頻為周期是1秒的分頻電路程序，即用2個計數(shù)200和一個計數(shù)150的三個計數(shù)器串聯(lián)而成，這樣200*200*150=6000000，即三個合起來計數(shù)6000000次剛好為1秒：
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity fenpin6M is
      port(cp:in std_logic;
           clk:out std_logic);
end fenpin12M;
Architecture fen  of fenpin12M is
  signal Q0,Q1,Q2:std_logic_vector(7 downto 0);
  signal c0,c1,c2:std_logic;
  begin
     process(cp,c0,c1)
       begin
         if cp'event and cp='1' then
              if Q0<199 then Q0<=Q0+1;
                 else Q0<="00000000";
              end if;
              if Q0=199 then c0<='1';
                 else c0<='0';
              end if;            
          end if;
       
        
          if c0'event and c0='1' then
              if Q1<149 then Q1<=Q1+1;
                 else Q1<="00000000";
              end if;
              if Q1=149 then c1<='1';
                 else c1<='0';
              end if;            
          end if;
                   
            if c1'event and c1='1' then
              if Q2<199 then Q2<=Q2+1;
                 else Q2<="00000000";
              end if;
              if Q2=199 then c2<='1';
                 else c2<='0';
              end if;            
          end if;
        
       end process;
       clk<=c2;
  end;

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