/****************************************/
//Code to transfer serial command to CH451, for EDA students in 7-Segments experiments
//3-line serial command:LDA,LCLK,LOAD,from CH451
//By you,2017.0922
//steps of transfer serial command:
// 1.recevie the parrel command from SEDLED_COMMAND
// 2.transfer the command via serial command
/****************************************************/
module CH451SPI_MODULE(rst,clk,command,command_idle,command_start,LDA,LCLK,LOAD);
parameter command_length=12;
input rst,clk; //system
input[command_length-1:0] command;
input command_start; //inidcate if the command start
//output
output LDA,LCLK,LOAD;
output command_idle;
//command
// state machine
reg[3:0] state;
parameter state_idle=4'h0;
parameter state_start=4'h1;// command start
parameter state_tran=4'h2;// transfer command
parameter state_judge=4'h3;// see if all command complete
parameter state_end=4'h4;
parameter state_rdy=4'h5;//load command
reg[7:0] count;// count number of commands
reg[command_length-1:0] current_command;
reg reg_LDA;
reg reg_LOAD;
/**************************************/
always@(negedge clk) // use negedge to avoid competion risk,
if(~rst)
begin
state<=state_idle;
count<=0;
reg_LDA<=1;
end
else
case(state)
state_idle: if(command_start) // if SPI module not busy,idle
state<=state_rdy;
else
state<=state_idle;
state_rdy: begin
current_command<=command;
state<=state_tran;
end// transfer the current command, one command only
state_tran:begin
if(count<command_length)
begin
reg_LDA<=current_command[0];
current_command<=(current_command>>1);
count<=count+1'b1;
end
else
begin
state<=state_end;
count<=0;
reg_LDA<=1;
end
end
state_end: state<=state_idle; // stop to here
default: state<=state_idle;
endcase
/*******************/
assign LDA=reg_LDA;
assign LCLK=clk;
always@(posedge clk)
if(~rst)
reg_LOAD<=1'b1;
else
begin
if(count==(command_length))
reg_LOAD<=1'b0;
else
reg_LOAD<=1'b1;
end
//assign LOAD=(count==(command_length-1))?1'b0:1'b1;
assign LOAD=reg_LOAD;// assign
assign command_idle=(state==state_idle)?1'b1:1'b0;
endmodule
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