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請(qǐng)問(wèn)為什讀寫(xiě)SRAM 是 用 data_out[7:0] = mem1[addr];
xxx = mem1[addr] 為什這樣可以取出SRAM 的資料
mem2[addr] = xxxx;
為什 mem1[addr] 可以代表 SRAM 裡的資料
//--------------------------------------------------------程式代碼
module idt71v416s15(data, addr, we_, oe_, cs_, ble_, bhe_);
inout [15:0] data;
input [17:0] addr;
input we_, oe_, cs_, bhe_, ble_;
reg [7:0] mem1[0:262143];
reg [7:0] mem2[0:262143];
time adr_chng,da_chng,we_fall,we_rise,cs_fall,cs_rise;
time oe_fall,oe_rise,ble_fall,ble_rise,bhe_fall,bhe_rise;
wire [15:0] data_in;
reg [15:0] data_out;
reg [15:0] temp1,temp2,temp3;
reg outen, out_en, in_en;
initial
begin
in_en = 1'b1;
if (cs_)
out_en = 1'b0;
end
// input/output control logic
//---------------------------
assign data = out_en ? data_out : 'hzzzz;
assign data_in = in_en ? data : 'hzzzz;
// read access
//------------
always @(addr)
if (cs_==0 & we_==1) begin //read
fork
if(~ble_)
#Taa data_out[7:0] = mem1[addr];
else #Taa data_out[7:0] = 'hzz;
if(~bhe_)
#Taa data_out[15:8] = mem2[addr];
else #Taa data_out[15:8] = 'hzz;
join
end
always @(addr)
begin
adr_chng = $time;
outen = 1'b0;
#Toh out_en = outen;
//---------------------------------------------
if (cs_==0 & we_==1) //read
begin
if (oe_==0)
begin
outen = 1'b1;
out_en = 1'b1;
end
end
//---------------------------------------------
if (cs_==0 & we_==0) //write
begin
if (oe_==0)
begin
outen = 1'b0;
out_en = 1'b0;
temp1 = data_in;
fork
if(~ble_)
#Tdw mem1[addr] = temp1[7:0];
if(~bhe_)
#Tdw mem2[addr] = temp1[15:8];
join
end
else
begin
outen = 1'b0;
out_en = 1'b0;
temp1 = data_in;
fork
if(~ble_)
#(Tdw-Toh) mem1[addr] = temp1[7:0];
if(~bhe_)
#(Tdw-Toh) mem2[addr] = temp1[15:8];
join
end
if(~ble_)
data_out[7:0] = mem1[addr];
else data_out[7:0] = 'hzz;
if(~bhe_)
data_out[15:8] = mem2[addr];
else data_out[15:8] = 'hzz;
end
end
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