自己做的19進制計數器，功能挺全
vhdl源程序如下:
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity jishuqijian is
- port(clk,clr:in std_logic;
- shi,ge:out std_logic_vector(6 downto 0);
- led:buffer std_logic);
- end entity ;
- architecture bhv of jishuqijian is
- signal clk1:std_logic;
- signal shi1,ge1:integer range 0 to 9;
- begin
- process(clk)
- variable num:integer range 1 to 25000000;
- begin
- if rising_edge(clk)then
- if num=25000000 then num:=1;clk1<=not clk1;
- else num:=num+1;
- end if;
- end if;
- end process;
- process (clk1,clr)
- begin
- if clr='1' then
- shi1<=1;
- ge1<=8;
- led<='0';
- elsif rising_edge (clk1) then
- if shi1=0 and ge1=0 then shi1<=1;ge1<=8;led<=not led;
- elsif shi1=1 and ge1=0 then shi1<=0;ge1<=9;
- else ge1<=ge1-1;
- end if ;
- end if;
- end process;
- process(shi1,ge1)
- begin
- case shi1 is
- when 0=>shi<="1000000";
- when 1=>shi<="1111001";
- when others=>shi<="1111111";
- end case ;
- case ge1 is
- when 0=>ge<="1000000";
- when 1=>ge<="1111001";
- when 2=>ge<="0100100";
- when 3=>ge<="0110000";
- when 4=>ge<="0011001";
- when 5=>ge<="0010010";
- when 6=>ge<="0000010";
- when 7=>ge<="1111000";
- when 8=>ge<="0000000";
- when 9=>ge<="0010000";
- when others=>ge<="1111111";
- end case ;
- end process;
- end bhv;
所有資料51hei提供下載:
19jishuqijian.zip
(7.53 MB, 下載次數: 18)
2019-7-3 11:43 上傳
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