基于FPGA的日式鐘程序設計

ID:584238 · 發表于 2019-7-15 10:09

在LED1602顯示時間 00：00：00
可以顯示溫度。

module lcd(clk,rs,miao0,miao1,fen2,fen3,shi4,shi5, wendu,rw, en,dat,rst_n);
input clk;
input rst_n;
input [3:0]miao0,miao1,fen2,fen3,shi4,shi5;
input [15:0] wendu;
output [7:0] dat;
output rs,rw,en;
reg e;
reg [7:0] dat;
reg rs;
reg [15:0] counter;
reg [4:0] next;
reg clkr;
reg [1:0] cnt;
parameter set0=4'h0;
parameter set1=4'h1;
parameter set2=4'h2;
parameter set3=4'h3;
parameter set4=4'h4;
parameter dat0=4'h5;
parameter dat1=4'h6;
parameter dat2=4'h7;
parameter dat3=4'h8;
parameter dat4=4'h9;
parameter dat5=4'hA;
parameter dat6=4'hB;
parameter dat7=4'hC;
parameter set5=5'hD;
parameter dat8=4'hE;
parameter dat9=4'hF;
parameter dat10=5'h10;
parameter dat11=5'h11;
parameter dat12=5'h12;
parameter nul=5'h13;
always @(posedge clk )
begin
counter=counter+1;
if(counter==16'h000f)
clkr=~clkr;
end
always @(posedge clkr)
begin
case(next)
set0: begin rs<=0; dat<=8'h38; next<=set1; end //設置為顯示2行，數據線8位 5x7點陣
set1: begin rs<=0; dat<=8'h0c; next<=set2; end //顯示功能開，無光標
set2: begin rs<=0; dat<=8'h6; next<=set3; end //光標右移，顯示屏不動
set3: begin rs<=0; dat<=8'h1; next<=set4; end //清屏
set4: begin rs<=0; dat<=8'h80; next<=dat0; end
dat0: begin rs<=1; dat<=shi5+8'h30; next<=dat1; end
dat1: begin rs<=1; dat<=shi4+8'h30; next<=dat2; end
dat2: begin rs<=1; dat<=":"; next<=dat3; end
dat3: begin rs<=1; dat<=fen3+8'h30; next<=dat4; end
dat4: begin rs<=1; dat<=fen2+8'h30; next<=dat5; end
dat5: begin rs<=1; dat<=":"; next<=dat6; end
dat6: begin rs<=1; dat<=miao1+8'h30; next<=dat7; end
dat7: begin rs<=1; dat<=miao0+8'h30; next<=set5; end
set5: begin rs<=0; dat<=8'hc0; next<=dat8; end
dat8: begin rs<=1;if (wendu[15]==0) begin dat<="+"; next<=dat9; end
else begin dat<="-"; next<=dat9; end
end
dat9: begin rs<=1;if (wendu[15]==0) begin dat<=((wendu[15:5]/8)%100)/10+8'h30; next<=dat10; end
else begin dat<=(((~wendu[14:5]+1)/8)%100)/10+8'h30; next<=dat10; end
end
dat10: begin rs<=1;if (wendu[15]==0) begin dat<=((wendu[15:5]/8)%100)%10+8'h30; next<=dat11; end
else begin dat<=(((~wendu[14:5]+1)/8)%100)%10+8'h30; next<=dat11; end
end
dat11: begin rs<=1; dat<=8'hdf; next<=dat12; end //顯示° 8'hdf
dat12: begin rs<=1; dat<="C"; next<=nul; end
//dat13: begin rs<=1; dat<=" "; next<=nul; end
nul: begin dat<=" ";next<=set4;end
default: next<=set0;
endcase
end
assign en=clkr|e;
assign rw=0; //只寫入
endmodule

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基于FPGA的日式鐘程序設計

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