四人搶答器VHDL編寫程序控制Quartus II

ID:422604 · 發(fā)表于 2019-11-27 08:49

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sirenqiangda is
   port(rst,rst2,clk,en,en1,ta,tb,lad,a,b,c,d,stop,add:in std_logic;
      ring,warn:out std_logic;
      digit1,digit2:out std_logic_vector(3 downto 0);
      a_out, b_out, c_out, d_out:buffer std_logic_vector(3 downto 0);
      states:buffer std_logic_vector(3 downto 0));
end sirenqiangda;

architecture one of sirenqiangda is
component qiangda is
   port(rst,clk,en,a,b,c,d:in std_logic;
         ring:out std_logic;
         state:out std_logic_vector(3 downto 0));
end component;
component jishu is
   port(rst,clk,en1,ta,tb,lad,stop:in std_logic;
         warn:out std_logic;
         digit1,digit2:out std_logic_vector(3 downto 0));
end component;
component jifen is
   port(rst2,clk,en,add:in std_logic;
      state:in std_logic_vector(3 downto 0);
      a_out, b_out, c_out, d_out:buffer std_logic_vector(3 downto 0));
end component;
begin
   U1: qiangda port map (rst,clk,en,a,b,c,d,ring,states);
   U2: jishu port map(rst,clk,en1,ta,tb,lad,stop,warn,digit1,digit2);
   U3: jifen port map (rst2,clk,en,add,states,a_out, b_out, c_out, d_out);
end one;

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四人搶答器VHDL編寫程序控制Quartus II

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