本帖最后由 WeTiGY 于 2016-11-25 23:26 編輯
實(shí)驗(yàn)四 七段數(shù)碼管顯示電路一、實(shí)驗(yàn)?zāi)康?/font> 實(shí)現(xiàn)十六進(jìn)制計(jì)數(shù)顯示。 二、硬件需求 EDA/SOPC實(shí)驗(yàn)箱一臺(tái)。 三、實(shí)驗(yàn)原理 七段數(shù)碼管分共陽極與共陰極兩種。共陽極數(shù)碼管其工作特點(diǎn)是，當(dāng)筆段電極接低電平，公共陽極接高電平時(shí)，相應(yīng)筆段可以發(fā)光。共陰極數(shù)碼管則與之相反，它是將發(fā)光二極管的陰極短接后作為公共陰極，當(dāng)驅(qū)動(dòng)信號(hào)為高電平、公共陰極接低電平時(shí)，才能發(fā)光。圖2-13為共陽極數(shù)碼管和共陰極數(shù)碼管的內(nèi)部結(jié)構(gòu)圖。
圖2-13 共陽極數(shù)碼管和共陰極數(shù)碼管的內(nèi)部結(jié)構(gòu)圖 用七段數(shù)碼管除了可以顯示0～9的阿拉伯?dāng)?shù)字外，還可以顯示一些英語字母。下表是常見的字母與7段顯示關(guān)系（共陰極數(shù)碼管）。 | file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image003.gif 段 字母 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
四、實(shí)驗(yàn)內(nèi)容 file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image004.giffile:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image004.gif編寫一個(gè)0～F輪換顯示的電路（注意：選用實(shí)驗(yàn)箱中的共陽數(shù)碼管DP1A，FPGA上P25引腳連接50MHz時(shí)鐘。實(shí)驗(yàn)時(shí)為了便于觀察，要將50MHz時(shí)鐘經(jīng)過分頻得到1Hz時(shí)鐘）。第一個(gè)為分頻模塊：
- module divider_module
- (
- CLK,f_Out
- );
- input CLK;
- output f_Out;
-
- parameter T1s=26'd50_000_000;
- reg [25:0]Count1;
-
- always @ ( posedge CLK )
- if( Count1 == T1s)
- Count1 <= 26'd0;
- else
- Count1 <= Count1 + 1'b1;
-
- reg rf_Out;
- always @ ( posedge CLK )
- if( Count1 >= 26'd0 && Count1 <= 26'd25_000_000)
- rf_Out <= 1'b0;
- else
- rf_Out <= 1'b1;
- assign f_Out = rf_Out;
- endmodule
第二個(gè)為數(shù)碼管模塊：
- module hex_module
- (
- f_out,hex
- );
- input f_out;
- output [6:0] hex;
-
- parameter _0=7'b0000001, _1=7'b1111001, _2=7'b0010010, _3=7'b0000011, _4=7'b1001100, _5=7'b0100100,
- _6=7'b0100000, _7=7'b0001111, _8=7'b0000000, _9=7'b0000100, _A=7'b0001000, _B=7'b1100000,
- _C=7'b0110001, _D=7'b1000010, _E=7'b0110000, _F=7'b0111000;
-
- reg [4:0] i;
- reg [6:0] rhex;
- always@(posedge f_out)
- case(i)
- 5'd0 : begin rhex<=_0; i<=i+1'b1; end //0
- 5'd1 : begin rhex<=_1; i<=i+1'b1; end //1
- 5'd2 : begin rhex<=_2; i<=i+1'b1; end //2
- 5'd3 : begin rhex<=_3; i<=i+1'b1; end //3
- 5'd4 : begin rhex<=_4; i<=i+1'b1; end //4
- 5'd5 : begin rhex<=_5; i<=i+1'b1; end //5
- 5'd6 : begin rhex<=_6; i<=i+1'b1; end //6
- 5'd7 : begin rhex<=_7; i<=i+1'b1; end //7
- 5'd8 : begin rhex<=_8; i<=i+1'b1; end //8
- 5'd9 : begin rhex<=_9; i<=i+1'b1; end //9
- 5'd10: begin rhex<=_A; i<=i+1'b1; end //A
- 5'd11: begin rhex<=_B; i<=i+1'b1; end //B
- 5'd12: begin rhex<=_C; i<=i+1'b1; end //C
- 5'd13: begin rhex<=_D; i<=i+1'b1; end //D
- 5'd14: begin rhex<=_E; i<=i+1'b1; end //E
- 5'd15: begin rhex<=_F; i<=i+1'b1; end //F
-
- default: begin rhex<=_F; i<=1'b0; end //F
- endcase
-
- assign hex=rhex;
- endmodule
第三個(gè)為頂層模塊，即將分頻模塊和數(shù)碼管模塊連接一起- module top_module
- (
- CLK,hex
- );
- input CLK;
- output [6:0] hex;
-
- wire f_out;
- divider_module u1
- (
- .CLK(CLK),
- .f_out(f_out)
- );
-
- hex_module u2
- (
- .f_out(f_out),
- .hex(hex)
- );
-
- endmodule
注：仿真使用20分頻
仿真圖：
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