iTOP-4412 # OK
U-Boot 2010.03-dirty (Nov 13 2015 - 02:04:50) for iTOP-4412 Android
CPU: SMDK4412-AP1.1 [e4412211]
APLL = 1000MHz, MPLL = 800MHz
ARM_CLOCK = 1000MHz
PMIC: S5M8767(VER5.0)
Board: iTOP-4412Quad
POP type: POP for C220
DRAM: 1023 MB
MMC: Count: 100
max_emmc_clock:40 MHZ
Set CLK to 400 KHz
EMMC CLOCK OUTPUT:: 400KHz -[div:50]
response timeout error : 00000104 cmd 8
response timeout error : 00000104 cmd 55
max_emmc_clock:40 MHZ
Input CLK [ 50 MHz] is higher than limit [40 MHZ]
Set CLK to 40000 KHz
EMMC clock output: 40000 KHz
max_emmc_clock:40 MHZ
Input CLK [ 50 MHz] is higher than limit [40 MHZ]
Set CLK to 40000 KHz
EMMC clock output: 40000 KHz
MMC0: 7456 MB
SD sclk_mmc is 400K HZ
SD sclk_mmc is 50000K HZ
SD sclk_mmc is 50000K HZ
MMC1: 15193 MB
*** Warning - using default environment
In: serial
Out: serial
Err: serial
eMMC OPEN Success.!!
!!!Notice!!!
!You must close eMMC boot Partition after all image writing!
!eMMC boot partition has continuity at image writing time.!
!So, Do not close boot partition, Before, all images is written.!
MMC read: dev # 0, block # 48, count 16 ...16 blocks read: OK
eMMC CLOSE Success.!!
Checking Boot Mode ... EMMC4.41
SYSTEM ENTER NORMAL BOOT MODE
Hit any key to stop autoboot: 0
reading kernel.. 1120, 12288
MMC read: dev # 0, block # 1120, count 12288 ...12288 blocks read: OK
completed
Boot with zImage
Wrong Ramdisk Image Format
[err] boot_get_ramdisk
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Linux version 3.0.15 (root@cym-virtual-machine) (gcc version 4.4.1 (Sourcery G++ Lite 2009q3-67) ) #7 SMP PREEMPT Thu Aug 11 11:48:39 CST 2016
[ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
[ 0.000000] CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine: SMDK4X12
[ 0.000000] **************************
[ 0.000000] reserve_panic_dump_area!!
[ 0.000000] **************************
[ 0.000000] Memory policy: ECC disabled, Data cache writealloc
[ 0.000000] CPU EXYNOS4412 (id 0xe4412211)
[ 0.000000] S3C24XX Clocks, Copyright 2004 Simtec Electronics
[ 0.000000] s3c_register_clksrc: clock audiocdclk has no registers set
[ 0.000000] audiocdclk: no parent clock specified
[ 0.000000] s3c_register_clksrc: clock armclk has no registers set
[ 0.000000] EXYNOS4: PLL settings, A=1000000000, M=800000000, E=96000000 V=350000000
[ 0.000000] EXYNOS4: ARMCLK=1000000000, DMC=400000000, ACLK200=24000000
[ 0.000000] ACLK160=160000000, ACLK133=133333333, ACLK100=100000000
[ 0.000000] EXYNOS4: ACLK400=24000000 ACLK266=800000000
[ 0.000000] uclk1: source is mout_mpll_user (6), rate is 100000000
[ 0.000000] uclk1: source is mout_mpll_user (6), rate is 100000000
[ 0.000000] uclk1: source is mout_mpll_user (6), rate is 100000000
[ 0.000000] uclk1: source is mout_mpll_user (6), rate is 100000000
[ 0.000000] sclk_csis: source is xusbxti (1), rate is 1500000
[ 0.000000] sclk_csis: source is xusbxti (1), rate is 1500000
[ 0.000000] sclk_cam0: source is xusbxti (1), rate is 1500000
[ 0.000000] sclk_cam1: source is xusbxti (1), rate is 1500000
[ 0.000000] sclk_fimc: source is xusbxti (1), rate is 1500000
[ 0.000000] sclk_fimc: source is xusbxti (1), rate is 1500000
[ 0.000000] sclk_fimc: source is xusbxti (1), rate is 1500000
[ 0.000000] sclk_fimc: source is xusbxti (1), rate is 1500000
[ 0.000000] sclk_fimd: source is xusbxti (1), rate is 1500000
[ 0.000000] sclk_fimd: source is xusbxti (1), rate is 1500000
[ 0.000000] sclk_mfc: source is mout_mfc0 (0), rate is 200000000
///后面還有很多信息，但是一次性發(fā)不上來
按照用戶手冊上來的，怎么也啟動(dòng)不了ubuntu，串口打印的信息一直，從頭到尾，不停地循環(huán)
怎么辦呀怎么辦
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