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1、Error: Can't continue timing simulation because delay annotation information for design is missing
這是因為未對工程進行綜合編譯，無法仿真。
解決辦法：編譯一次
2、Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
CLK沒有定義成時鐘信號
解決辦法：pin lanner中將clk定義到晶振引腳或clk接到某個時鐘信號（可以使pll輸出）上
3、Warning: Converted tri-state buffer "init_module:j2|initial_control_module:u1|wr_data[0]" feeding internal logic into a wire
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